pub enum Inst {
Show 111 variants
Lb {
rd: u8,
rs1: u8,
imm: i32,
},
Lh {
rd: u8,
rs1: u8,
imm: i32,
},
Lw {
rd: u8,
rs1: u8,
imm: i32,
},
Ld {
rd: u8,
rs1: u8,
imm: i32,
},
Lbu {
rd: u8,
rs1: u8,
imm: i32,
},
Lhu {
rd: u8,
rs1: u8,
imm: i32,
},
Lwu {
rd: u8,
rs1: u8,
imm: i32,
},
Sb {
rs1: u8,
rs2: u8,
imm: i32,
},
Sh {
rs1: u8,
rs2: u8,
imm: i32,
},
Sw {
rs1: u8,
rs2: u8,
imm: i32,
},
Sd {
rs1: u8,
rs2: u8,
imm: i32,
},
Addi {
rd: u8,
rs1: u8,
imm: i32,
},
Slti {
rd: u8,
rs1: u8,
imm: i32,
},
Sltiu {
rd: u8,
rs1: u8,
imm: i32,
},
Andi {
rd: u8,
rs1: u8,
imm: i32,
},
Ori {
rd: u8,
rs1: u8,
imm: i32,
},
Xori {
rd: u8,
rs1: u8,
imm: i32,
},
Slli {
rd: u8,
rs1: u8,
shamt: u8,
},
Srli {
rd: u8,
rs1: u8,
shamt: u8,
},
Srai {
rd: u8,
rs1: u8,
shamt: u8,
},
Addiw {
rd: u8,
rs1: u8,
imm: i32,
},
Slliw {
rd: u8,
rs1: u8,
shamt: u8,
},
Srliw {
rd: u8,
rs1: u8,
shamt: u8,
},
Sraiw {
rd: u8,
rs1: u8,
shamt: u8,
},
Add {
rd: u8,
rs1: u8,
rs2: u8,
},
Sub {
rd: u8,
rs1: u8,
rs2: u8,
},
Sll {
rd: u8,
rs1: u8,
rs2: u8,
},
Srl {
rd: u8,
rs1: u8,
rs2: u8,
},
Sra {
rd: u8,
rs1: u8,
rs2: u8,
},
Slt {
rd: u8,
rs1: u8,
rs2: u8,
},
Sltu {
rd: u8,
rs1: u8,
rs2: u8,
},
Xor {
rd: u8,
rs1: u8,
rs2: u8,
},
Or {
rd: u8,
rs1: u8,
rs2: u8,
},
And {
rd: u8,
rs1: u8,
rs2: u8,
},
Addw {
rd: u8,
rs1: u8,
rs2: u8,
},
Subw {
rd: u8,
rs1: u8,
rs2: u8,
},
Sllw {
rd: u8,
rs1: u8,
rs2: u8,
},
Srlw {
rd: u8,
rs1: u8,
rs2: u8,
},
Sraw {
rd: u8,
rs1: u8,
rs2: u8,
},
Mul {
rd: u8,
rs1: u8,
rs2: u8,
},
Mulh {
rd: u8,
rs1: u8,
rs2: u8,
},
Mulhsu {
rd: u8,
rs1: u8,
rs2: u8,
},
Mulhu {
rd: u8,
rs1: u8,
rs2: u8,
},
Div {
rd: u8,
rs1: u8,
rs2: u8,
},
Divu {
rd: u8,
rs1: u8,
rs2: u8,
},
Rem {
rd: u8,
rs1: u8,
rs2: u8,
},
Remu {
rd: u8,
rs1: u8,
rs2: u8,
},
Mulw {
rd: u8,
rs1: u8,
rs2: u8,
},
Divw {
rd: u8,
rs1: u8,
rs2: u8,
},
Divuw {
rd: u8,
rs1: u8,
rs2: u8,
},
Remw {
rd: u8,
rs1: u8,
rs2: u8,
},
Remuw {
rd: u8,
rs1: u8,
rs2: u8,
},
Clz {
rd: u8,
rs1: u8,
},
Clzw {
rd: u8,
rs1: u8,
},
Ctz {
rd: u8,
rs1: u8,
},
Ctzw {
rd: u8,
rs1: u8,
},
Cpop {
rd: u8,
rs1: u8,
},
Cpopw {
rd: u8,
rs1: u8,
},
SextB {
rd: u8,
rs1: u8,
},
SextH {
rd: u8,
rs1: u8,
},
ZextH {
rd: u8,
rs1: u8,
},
Rev8 {
rd: u8,
rs1: u8,
},
OrcB {
rd: u8,
rs1: u8,
},
Min {
rd: u8,
rs1: u8,
rs2: u8,
},
Minu {
rd: u8,
rs1: u8,
rs2: u8,
},
Max {
rd: u8,
rs1: u8,
rs2: u8,
},
Maxu {
rd: u8,
rs1: u8,
rs2: u8,
},
Andn {
rd: u8,
rs1: u8,
rs2: u8,
},
Orn {
rd: u8,
rs1: u8,
rs2: u8,
},
Xnor {
rd: u8,
rs1: u8,
rs2: u8,
},
Rol {
rd: u8,
rs1: u8,
rs2: u8,
},
Ror {
rd: u8,
rs1: u8,
rs2: u8,
},
Rolw {
rd: u8,
rs1: u8,
rs2: u8,
},
Rorw {
rd: u8,
rs1: u8,
rs2: u8,
},
Rori {
rd: u8,
rs1: u8,
shamt: u8,
},
Roriw {
rd: u8,
rs1: u8,
shamt: u8,
},
Sh1add {
rd: u8,
rs1: u8,
rs2: u8,
},
Sh2add {
rd: u8,
rs1: u8,
rs2: u8,
},
Sh3add {
rd: u8,
rs1: u8,
rs2: u8,
},
Sh1adduw {
rd: u8,
rs1: u8,
rs2: u8,
},
Sh2adduw {
rd: u8,
rs1: u8,
rs2: u8,
},
Sh3adduw {
rd: u8,
rs1: u8,
rs2: u8,
},
Adduw {
rd: u8,
rs1: u8,
rs2: u8,
},
Slliuw {
rd: u8,
rs1: u8,
shamt: u8,
},
Bclr {
rd: u8,
rs1: u8,
rs2: u8,
},
Bset {
rd: u8,
rs1: u8,
rs2: u8,
},
Binv {
rd: u8,
rs1: u8,
rs2: u8,
},
Bext {
rd: u8,
rs1: u8,
rs2: u8,
},
Bclri {
rd: u8,
rs1: u8,
shamt: u8,
},
Bseti {
rd: u8,
rs1: u8,
shamt: u8,
},
Binvi {
rd: u8,
rs1: u8,
shamt: u8,
},
Bexti {
rd: u8,
rs1: u8,
shamt: u8,
},
CzeroEqz {
rd: u8,
rs1: u8,
rs2: u8,
},
CzeroNez {
rd: u8,
rs1: u8,
rs2: u8,
},
Lui {
rd: u8,
imm: i32,
},
Auipc {
rd: u8,
imm: i32,
},
Jal {
rd: u8,
imm: i32,
},
Jalr {
rd: u8,
rs1: u8,
imm: i32,
},
Beq {
rs1: u8,
rs2: u8,
imm: i32,
},
Bne {
rs1: u8,
rs2: u8,
imm: i32,
},
Blt {
rs1: u8,
rs2: u8,
imm: i32,
},
Bge {
rs1: u8,
rs2: u8,
imm: i32,
},
Bltu {
rs1: u8,
rs2: u8,
imm: i32,
},
Bgeu {
rs1: u8,
rs2: u8,
imm: i32,
},
Fence,
FenceI,
Trap,
EcallJar,
Ecalli {
imm: i32,
},
Fallthrough,
Reserved {
raw: u32,
},
}Expand description
Decoded RV instruction in named-variant form.
One variant per RV operation we accept. Field layout is per the
RV unprivileged spec. Immediate fields are pre-sign-extended to
i32.
Variants§
Lb
Lh
Lw
Ld
Lbu
Lhu
Lwu
Sb
Sh
Sw
Sd
Addi
Slti
Sltiu
Andi
Ori
Xori
Slli
Srli
Srai
Addiw
Slliw
Srliw
Sraiw
Add
Sub
Sll
Srl
Sra
Slt
Sltu
Xor
Or
And
Addw
Subw
Sllw
Srlw
Sraw
Mul
Mulh
Mulhsu
Mulhu
Div
Divu
Rem
Remu
Mulw
Divw
Divuw
Remw
Remuw
Clz
Clzw
Ctz
Ctzw
Cpop
Cpopw
SextB
SextH
ZextH
Rev8
OrcB
Min
Minu
Max
Maxu
Andn
Orn
Xnor
Rol
Ror
Rolw
Rorw
Rori
Roriw
Sh1add
Sh2add
Sh3add
Sh1adduw
Sh2adduw
Sh3adduw
Adduw
Slliuw
Bclr
Bset
Binv
Bext
Bclri
Bseti
Binvi
Bexti
CzeroEqz
CzeroNez
Lui
Auipc
auipc rd, imm — rd = pc + (imm << 12). With code mapped at
CODE_BASE, pc is the guest VA, so the recompiler folds this
to a compile-time constant. imm holds the already-shifted
upper-20 value (same shape as Lui).
Jal
jal rd, off — rd = pc + sizeof(jal); pc = pc + off. Used
for static jumps (rd = x0, = c.j) and direct calls
(rd = ra, saving the return address natively).
Jalr
jalr rd, rs1, imm — rd = pc + sizeof;
target_va = (rs1 + imm) & 0xFFFF_FFFF (32-bit wrap). The
runtime validates the target is a basic-block start (else Panic)
and dispatches. Used for returns (jalr x0, ra, 0) and
indirect calls.
Beq
Bne
Blt
Bge
Bltu
Bgeu
Fence
fence — decoded but treated as no-op (PVM2 is single-threaded).
FenceI
fence.i — same.
Trap
custom-0 funct3=000: unconditional execution abort.
EcallJar
custom-0 funct3=001: jar management op / dynamic CALL.
Ecalli
custom-0 funct3=010: host-call with 20-bit signed immediate.
Fallthrough
custom-0 funct3=100: terminator no-op. Acts as a basic-block
start at the next byte. Linker injects this before branch / call
targets that aren’t naturally post-terminator.
Reserved
Decoder accepted the wire bits but the encoding is reserved by PVM2 (AUIPC, standard ECALL/EBREAK, CSR, atomics, FP, …). Programs containing this are rejected at deblob.
Implementations§
Source§impl Inst
impl Inst
Sourcepub fn uses_reserved_reg(&self) -> bool
pub fn uses_reserved_reg(&self) -> bool
True iff this instruction names a reserved register in any of its
register fields. The valid PVM2 registers are x0, x1..x15 (RV64E’s
full file, including x3/x4); reserved are only x16..x31, which
do not exist in RV64E — a 16-register base — so naming one is an
illegal, standard-RV encoding. Such an instruction decodes as
Reserved and panics if executed (lazy). Immediate bits that happen
to alias a reserved register are not registers and are ignored —
each variant binds exactly its real register fields. This match is
the single source of truth both consensus engines route through (the
interpreter via decode, the recompiler via
word_uses_reserved_reg); the lack of a wildcard arm means a
future Inst variant won’t compile until classified.