Module instruction 

RV64+C+custom-0 instruction decoder for PVM2.

Decodes a 16-bit-aligned cursor into (Inst, byte_length). Compressed (RVC) instructions are decompressed at decode time into their 32-bit equivalents so the rest of the pipeline sees uniform Inst values; the returned byte_length (2 or 4) is the wire length, used to advance PC.

ISA coverage matches the PVM2 spec (~/docs/pvm-isa/05-pvm2-rv-diff.md and 06-pvm2-pvm-diff.md):

RV64I base + M + C + Zbb + Zba + Zbs + Zicond + Zicclsm

• custom-0 ops: trap / ecall.jar / ecalli

Forbidden encodings (per PVM2-Base divergences):

• Standard ECALL / EBREAK (RV SYSTEM major) — decoder returns Reserved. PVM2’s ecall lives in custom-0 instead.
• CSR ops, atomics, FP, vector — Reserved.
• Any reg field of x16..x31 — Reserved; x3/x4 are valid RV64E registers and route through the spilled-register path.

Enums

Inst

Decoded RV instruction in named-variant form.

Functions

decode

Decode a single instruction starting at bytes[0].

word_uses_reserved_reg

Reserved-register predicate on a raw 4-byte word, for the recompiler (which dispatches on raw words rather than building an Inst, and runs on the cold-compile hot path — so this must not re-decode).

word_uses_spilled_reg

Spilled-register predicate on a raw 4-byte word, for the recompiler.