Expand description
RV64E-subset program generator.
Two modes, sharing one boundary-biased operand pool:
enumerate_boundary— deterministic, near-exhaustive over each op × boundary-operand combination. This is what guarantees the high-value corners appear (e.g.div x?, INT_MIN, -1).Gen::random_program— random instruction sequences for cross-op / cross-state breadth, seeded for reproducibility.
Every generated program is total by construction: register-only,
straight-line, over x0–x15 minus the spilled (x3/x4) and x6/x7 (left at 0 so
their signature slots are deterministic), ending in
encode::signature_epilogue. So it always halts cleanly on a conformant
engine — and on the oracle — with a defined register signature. (The div
corners are included: RISC-V defines INT_MIN/-1 as a value, so the oracle
and interpreter produce one; only a buggy recompiler diverges.)
v1 emits register-only ops (no loads/stores/branches — those want a memory
window / control flow and come later); this already covers the
value-domain edge cases that matter most (div overflow, shift masking, W-op
sign-extension, mulhsu, Zbb corners).
Structs§
- Gen
- Random program generator.
- XorShift64
- Small, fast, deterministic PRNG (xorshift64* — state never zero).
Constants§
- IMM20S
- Boundary 20-bit upper immediates (for
lui/auipc). - IMMS
- Boundary 12-bit-signed immediates (for I-type ALU).
- OPERANDS
- Boundary-biased operand pool — the values bugs hide at.
- SHAMTS
- Boundary shift amounts — includes the out-of-range 64/65 that exercise the
& 63/& 31masking both engines (must) perform.
Functions§
- enumerate_
boundary - Deterministic boundary enumeration. For each register-only op, emit one program per relevant boundary-operand combination, seeding source registers x8/x9 and writing the result to x10. Guarantees the corner cases appear.