Module encode 

RV64E-subset instruction encoders — the single source the generator and the decode round-trip test both drive off.

The two existing x3/x4 test files (javm-recompiler-x86/tests/x3_x4_spill.rs and javm-bench/tests/x3_x4_differential.rs) each hand-rolled a handful of ad-hoc encoders. This centralizes them and extends to the full implemented ISA via the OPS spec table, validated against javm_exec::decode in the tests below (every op must round-trip to a non-Reserved instruction).

Structs

OpSpec

One implemented instruction: enough to encode it from operands.

Enums

Fmt

Instruction format — selects how encode_op places operands.

Constants

HALT

ecalli 0 — HostCall(0), the clean trampoline halt both engines surface as exit_reason = 4. Appended by the replay harness, not stored in vectors.

OPS

Every instruction family the generator can emit. Validated against the decoder in round_trip_all_ops (each must decode to a non-Reserved instruction). Excludes terminators (ecalli/trap/fallthrough), fence, and anything reserved (SYSTEM, x3/x4, x16–31).

SIG_BASE_REG

Scratch base register for the signature stores. x3 is spilled — it is not in the captured set (slots 0..=12) and is invocation-local (dropped at exit), so clobbering it is invisible to the differential, and both engines agree on x3/x4 spill semantics (the x3_x4_differential net). Using it as the store base leaves every captured register untouched, so the stored values are the program’s exact post-body register file.

SIG_BYTES

Byte length of the register signature: one little-endian u64 per captured slot. Fits in a single page and in SCRATCHPAD_HEAD_LEN (128).

SIG_REGS

Number of host-mapped register slots captured by the signature (slots 0..=12 → x1, x2, x5, x6, x7, x8–x15; see crate::oracle::slot_to_xreg).

SIG_XREGS

The x-register stored at signature slot i (the inverse of javm_exec::regs::reg_slot_or_ff, matching crate::oracle::slot_to_xreg). Slot 7 = x10 (the former fold return_value). The epilogue stores each at byte offset 8*i of the signature region.

Functions

add

addi

beq

div

enc

Pack instruction words into a little-endian byte stream.

encode_op

Encode op with the given operands. Operands not used by the format are ignored (e.g. rs2 for Fmt::I, imm for Fmt::Unary). For shift formats the low bits of imm are the shift amount; for Fmt::U, imm is the 20-bit upper immediate.

ld

li64

Materialize an arbitrary value into rd using only rd (no scratch register): build MSB-first in 11-bit chunks via addi/slli. Each addi adds an 11-bit (always non-negative) chunk into freshly-zeroed low bits.

lui

mulhsu

rem

rori

sd

signature_epilogue

Emit the signature epilogue (no terminator): materialize sig_base into the scratch base register, then sd each captured register to sig_base + 8*i. sig_base is the guest VA the scratchpad (slot[0]) DataCap maps at; the guest’s stores CoW the region’s pages, and the host reads the effective bytes back as the run’s lossless register signature (vs the old lossy x10 fold).

slli

sub

xor